1. Field of the invention
The present invention relates in general to a method for making a contact hole during manufacture of a semiconductor device and more particularly to a method resulting in improvement in securing clearance in a micro contact hole.
2. Description of the Prior Art
Generally, as a semiconductor is highly integrated, cell area must become smaller. For the purpose of scaling a cell down, it is required to shorten gate length or to reduce the size of contact. In this regard, specification for designing highly integrated semiconductor devices are moving in a direction of greater stringency, so that it is becoming more difficult to form a contact hole in a small space.
Hereinafter, description of a conventional method for making a contact hole is given for better understanding of the background of the invention with reference to the drawings.
Referring initially to FIG. 1, a conventional embodiment is described briefly. This figure shows a conventional contact hole in a plan view. As shown in FIG. 1, a plurality of parallel, first spaced-apart polysilicon films 2 are perpendicular to a plurality of second parallel, spaced-apart polysilicon films 4.
Referring now to FIG. 2, there is a cross-sectional elevation view of the conventional embodiment of FIG. 1 taken generally through section line A--A' of FIG. 1. This drawing shows the relationship between first polysilicon film 2 and second polysilicon film 4 and a lower layer. As shown in FIG. 2, a first oxide film 1 is covered with the first polysilicon film 2 on which a second oxide film 3, the second polysilicon film 4 and a third oxide film 5 are formed in due order. This resulting structure is mounted on an impurity diffusion region. Using a mask, the first, second and third oxide film are subjected to the treatment of etching so as to form a contact hole. However, this conventional method has a disadvantage such that on micro-patterning, clearance is not sufficient. That is is spaces a and b where the method are carried out is very small, as shown in FIG. 2.
Since the conventional method has very small clearances, even a small error in mask arrangement causes such a problem that an inter-layer conductive material can be exposed to the contact hole. FIG. 3 shows misaligned mask arrangement in an embodiment according to the conventional method. FIG. 4, which is a cross-sectional elevation view of the conventional embodiment of FIG. 3 taken generally through section line A--A' of FIG. 3, shows that inter-layer conductive materials 2' and 4' are exposed to the contact hole and will be connected with a conductive layer to be deposited later.